MAC Architecture – Accumulator Based on Booth Encoding Parallel Multiplier

The MAC provides high speed multiplication with accumulative addition. In this paper, we study the various parallel MAC architectures and then implement a design of parallel MAC based on some booth encodings such as radix-4 booth encoder and some final adders such as CLA, Kogge stone adder and then compare their performance characteristics. The one most effective way to increase the speed of a multiplier is to reduce the number of the partial products. Although the number of partial products can be reduced with a higher radix booth encoder, but the number of hard multiples that are expensive to generate also increases simultaneously. To increase the speed and performance, many parallel MAC architectures have been proposed. Parallelism in obtaining partial products is the most common technique used in this implemented architecture.